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[HALPC98] Improve TSC calibration routine (#8860)

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Do not rely on a hardcoded ASM instruction offset.

Addendum to commit 45e6d49a29.
CORE-17977
This commit is contained in:
Dmitry Borisov
2026-05-06 19:20:17 +06:00
committed by GitHub
parent af895a116b
commit 82ef7e5d04
2 changed files with 5 additions and 2 deletions
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2
hal/halx86/pc98/delay.S
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@@ -97,6 +97,8 @@ _KeStallExecutionProcessor@4:
* Force the in-order execution of the RDTSC instruction.
* HAL will overwrite this with a no-op instruction on older processors.
*/
PUBLIC _HalpStallExecutionSerialize
_HalpStallExecutionSerialize:
xor eax, eax
cpuid

5
hal/halx86/pc98/delay.c
View File

@@ -25,6 +25,7 @@ HalpTscCalibrationISR(VOID);
extern volatile ULONG TscCalibrationPhase;
extern ULONG64 TscCalibrationArray[NUM_SAMPLES];
extern UCHAR HalpStallExecutionSerialize;
/* FUNCTIONS *****************************************************************/
@@ -33,7 +34,7 @@ CODE_SEG("INIT")
VOID
HalpPrepareStallExecution(VOID)
{
PUCHAR Instruction = (PUCHAR)((ULONG_PTR)KeStallExecutionProcessor + 1);
PUCHAR Instruction = &HalpStallExecutionSerialize;
PKPRCB Prcb = KeGetCurrentPrcb();
/* xor eax, eax; cpuid */
@@ -48,7 +49,7 @@ HalpPrepareStallExecution(VOID)
* Intel "Using the RDTSC Instruction for Performance Monitoring".
*
* Patch the KeStallExecutionProcessor function to remove the serializing instruction
* for the Pentium and Pentium MMX processors.
* for the Pentium and Pentium MMX processors because the CPUID instruction is slow.
*/
if ((Prcb->CpuType < 6) && !strcmp(Prcb->VendorString, "GenuineIntel"))
{