From 82ef7e5d04b810f87f2b78bd5776d163a03799bc Mon Sep 17 00:00:00 2001 From: Dmitry Borisov Date: Wed, 6 May 2026 19:20:17 +0600 Subject: [PATCH] [HALPC98] Improve TSC calibration routine (#8860) Do not rely on a hardcoded ASM instruction offset. Addendum to commit 45e6d49a29dcc76ffad0cc11a5ea0526d1da09cf. CORE-17977 --- hal/halx86/pc98/delay.S | 2 ++ hal/halx86/pc98/delay.c | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/hal/halx86/pc98/delay.S b/hal/halx86/pc98/delay.S index b003373e680..7d28afaff17 100644 --- a/hal/halx86/pc98/delay.S +++ b/hal/halx86/pc98/delay.S @@ -97,6 +97,8 @@ _KeStallExecutionProcessor@4: * Force the in-order execution of the RDTSC instruction. * HAL will overwrite this with a no-op instruction on older processors. */ +PUBLIC _HalpStallExecutionSerialize +_HalpStallExecutionSerialize: xor eax, eax cpuid diff --git a/hal/halx86/pc98/delay.c b/hal/halx86/pc98/delay.c index c8a812e7d51..fbf226b7027 100644 --- a/hal/halx86/pc98/delay.c +++ b/hal/halx86/pc98/delay.c @@ -25,6 +25,7 @@ HalpTscCalibrationISR(VOID); extern volatile ULONG TscCalibrationPhase; extern ULONG64 TscCalibrationArray[NUM_SAMPLES]; +extern UCHAR HalpStallExecutionSerialize; /* FUNCTIONS *****************************************************************/ @@ -33,7 +34,7 @@ CODE_SEG("INIT") VOID HalpPrepareStallExecution(VOID) { - PUCHAR Instruction = (PUCHAR)((ULONG_PTR)KeStallExecutionProcessor + 1); + PUCHAR Instruction = &HalpStallExecutionSerialize; PKPRCB Prcb = KeGetCurrentPrcb(); /* xor eax, eax; cpuid */ @@ -48,7 +49,7 @@ HalpPrepareStallExecution(VOID) * Intel "Using the RDTSC Instruction for Performance Monitoring". * * Patch the KeStallExecutionProcessor function to remove the serializing instruction - * for the Pentium and Pentium MMX processors. + * for the Pentium and Pentium MMX processors because the CPUID instruction is slow. */ if ((Prcb->CpuType < 6) && !strcmp(Prcb->VendorString, "GenuineIntel")) {