diff --git a/drivers/network/dd/e1000/e1000hw.h b/drivers/network/dd/e1000/e1000hw.h index 994be06067f..086842ce68a 100644 --- a/drivers/network/dd/e1000/e1000hw.h +++ b/drivers/network/dd/e1000/e1000hw.h @@ -56,10 +56,10 @@ typedef enum _E1000_RCVBUF_SIZE /* 3.2.3 Receive Descriptor Format */ -#define E1000_RDESC_STATUS_PIF (1 << 7) /* Passed in-exact filter */ -#define E1000_RDESC_STATUS_IXSM (1 << 2) /* Ignore Checksum Indication */ -#define E1000_RDESC_STATUS_EOP (1 << 1) /* End of Packet */ -#define E1000_RDESC_STATUS_DD (1 << 0) /* Descriptor Done */ +#define E1000_RDESC_STATUS_PIF (1U << 7) /* Passed in-exact filter */ +#define E1000_RDESC_STATUS_IXSM (1U << 2) /* Ignore Checksum Indication */ +#define E1000_RDESC_STATUS_EOP (1U << 1) /* End of Packet */ +#define E1000_RDESC_STATUS_DD (1U << 0) /* Descriptor Done */ typedef struct _E1000_RECEIVE_DESCRIPTOR { @@ -76,12 +76,12 @@ typedef struct _E1000_RECEIVE_DESCRIPTOR /* 3.3.3 Legacy Transmit Descriptor Format */ -#define E1000_TDESC_CMD_IDE (1 << 7) /* Interrupt Delay Enable */ -#define E1000_TDESC_CMD_RS (1 << 3) /* Report Status */ -#define E1000_TDESC_CMD_IFCS (1 << 1) /* Insert FCS */ -#define E1000_TDESC_CMD_EOP (1 << 0) /* End Of Packet */ +#define E1000_TDESC_CMD_IDE (1U << 7) /* Interrupt Delay Enable */ +#define E1000_TDESC_CMD_RS (1U << 3) /* Report Status */ +#define E1000_TDESC_CMD_IFCS (1U << 1) /* Insert FCS */ +#define E1000_TDESC_CMD_EOP (1U << 0) /* End Of Packet */ -#define E1000_TDESC_STATUS_DD (1 << 0) /* Descriptor Done */ +#define E1000_TDESC_STATUS_DD (1U << 0) /* Descriptor Done */ typedef struct _E1000_TRANSMIT_DESCRIPTOR { @@ -148,23 +148,23 @@ C_ASSERT(sizeof(E1000_TRANSMIT_DESCRIPTOR) == 16); /* E1000_REG_CTRL */ -#define E1000_CTRL_LRST (1 << 3) /* Link Reset */ -#define E1000_CTRL_ASDE (1 << 5) /* Auto-Speed Detection Enable */ -#define E1000_CTRL_SLU (1 << 6) /* Set Link Up */ -#define E1000_CTRL_RST (1 << 26) /* Device Reset, Self clearing */ -#define E1000_CTRL_VME (1 << 30) /* VLAN Mode Enable */ +#define E1000_CTRL_LRST (1U << 3) /* Link Reset */ +#define E1000_CTRL_ASDE (1U << 5) /* Auto-Speed Detection Enable */ +#define E1000_CTRL_SLU (1U << 6) /* Set Link Up */ +#define E1000_CTRL_RST (1U << 26) /* Device Reset, Self clearing */ +#define E1000_CTRL_VME (1U << 30) /* VLAN Mode Enable */ /* E1000_REG_STATUS */ -#define E1000_STATUS_FD (1 << 0) /* Full Duplex Indication */ -#define E1000_STATUS_LU (1 << 1) /* Link Up Indication */ +#define E1000_STATUS_FD (1U << 0) /* Full Duplex Indication */ +#define E1000_STATUS_LU (1U << 1) /* Link Up Indication */ #define E1000_STATUS_SPEEDSHIFT 6 /* Link speed setting */ -#define E1000_STATUS_SPEEDMASK (3 << E1000_STATUS_SPEEDSHIFT) +#define E1000_STATUS_SPEEDMASK (3U << E1000_STATUS_SPEEDSHIFT) /* E1000_REG_EERD */ -#define E1000_EERD_START (1 << 0) /* Start Read*/ -#define E1000_EERD_DONE (1 << 4) /* Read Done */ +#define E1000_EERD_START (1U << 0) /* Start Read*/ +#define E1000_EERD_DONE (1U << 4) /* Read Done */ #define E1000_EERD_ADDR_SHIFT 8 #define E1000_EERD_DATA_SHIFT 16 @@ -173,19 +173,19 @@ C_ASSERT(sizeof(E1000_TRANSMIT_DESCRIPTOR) == 16); #define E1000_MDIC_REGADD_SHIFT 16 /* PHY Register Address */ #define E1000_MDIC_PHYADD_SHIFT 21 /* PHY Address (1=Gigabit, 2=PCIe) */ #define E1000_MDIC_PHYADD_GIGABIT 1 -#define E1000_MDIC_OP_READ (2 << 26) /* Opcode */ -#define E1000_MDIC_R (1 << 28) /* Ready Bit */ -#define E1000_MDIC_E (1 << 30) /* Error */ +#define E1000_MDIC_OP_READ (2U << 26) /* Opcode */ +#define E1000_MDIC_R (1U << 28) /* Ready Bit */ +#define E1000_MDIC_E (1U << 30) /* Error */ /* E1000_REG_IMS */ -#define E1000_IMS_TXDW (1 << 0) /* Transmit Descriptor Written Back */ -#define E1000_IMS_TXQE (1 << 1) /* Transmit Queue Empty */ -#define E1000_IMS_LSC (1 << 2) /* Sets mask for Link Status Change */ -#define E1000_IMS_RXDMT0 (1 << 4) /* Receive Descriptor Minimum Threshold Reached */ -#define E1000_IMS_RXT0 (1 << 7) /* Receiver Timer Interrupt */ -#define E1000_IMS_TXD_LOW (1 << 15) /* Transmit Descriptor Low Threshold hit */ -#define E1000_IMS_SRPD (1 << 16) /* Small Receive Packet Detection */ +#define E1000_IMS_TXDW (1U << 0) /* Transmit Descriptor Written Back */ +#define E1000_IMS_TXQE (1U << 1) /* Transmit Queue Empty */ +#define E1000_IMS_LSC (1U << 2) /* Sets mask for Link Status Change */ +#define E1000_IMS_RXDMT0 (1U << 4) /* Receive Descriptor Minimum Threshold Reached */ +#define E1000_IMS_RXT0 (1U << 7) /* Receiver Timer Interrupt */ +#define E1000_IMS_TXD_LOW (1U << 15) /* Transmit Descriptor Low Threshold hit */ +#define E1000_IMS_SRPD (1U << 16) /* Small Receive Packet Detection */ /* E1000_REG_ITR */ @@ -194,31 +194,31 @@ C_ASSERT(sizeof(E1000_TRANSMIT_DESCRIPTOR) == 16); /* E1000_REG_RCTL */ -#define E1000_RCTL_EN (1 << 1) /* Receiver Enable */ -#define E1000_RCTL_SBP (1 << 2) /* Store Bad Packets */ -#define E1000_RCTL_UPE (1 << 3) /* Unicast Promiscuous Enabled */ -#define E1000_RCTL_MPE (1 << 4) /* Multicast Promiscuous Enabled */ -#define E1000_RCTL_BAM (1 << 15) /* Broadcast Accept Mode */ +#define E1000_RCTL_EN (1U << 1) /* Receiver Enable */ +#define E1000_RCTL_SBP (1U << 2) /* Store Bad Packets */ +#define E1000_RCTL_UPE (1U << 3) /* Unicast Promiscuous Enabled */ +#define E1000_RCTL_MPE (1U << 4) /* Multicast Promiscuous Enabled */ +#define E1000_RCTL_BAM (1U << 15) /* Broadcast Accept Mode */ #define E1000_RCTL_BSIZE_SHIFT 16 -#define E1000_RCTL_PMCF (1 << 23) /* Pass MAC Control Frames */ -#define E1000_RCTL_BSEX (1 << 25) /* Buffer Size Extension */ -#define E1000_RCTL_SECRC (1 << 26) /* Strip Ethernet CRC from incoming packet */ +#define E1000_RCTL_PMCF (1U << 23) /* Pass MAC Control Frames */ +#define E1000_RCTL_BSEX (1U << 25) /* Buffer Size Extension */ +#define E1000_RCTL_SECRC (1U << 26) /* Strip Ethernet CRC from incoming packet */ #define E1000_RCTL_FILTER_BITS (E1000_RCTL_SBP | E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM | E1000_RCTL_PMCF) /* E1000_REG_TCTL */ -#define E1000_TCTL_EN (1 << 1) /* Transmit Enable */ -#define E1000_TCTL_PSP (1 << 3) /* Pad Short Packets */ +#define E1000_TCTL_EN (1U << 1) /* Transmit Enable */ +#define E1000_TCTL_PSP (1U << 3) /* Pad Short Packets */ /* E1000_REG_TIPG */ -#define E1000_TIPG_IPGT_DEF (10 << 0) /* IPG Transmit Time */ -#define E1000_TIPG_IPGR1_DEF (10 << 10) /* IPG Receive Time 1 */ -#define E1000_TIPG_IPGR2_DEF (10 << 20) /* IPG Receive Time 2 */ +#define E1000_TIPG_IPGT_DEF (10U << 0) /* IPG Transmit Time */ +#define E1000_TIPG_IPGR1_DEF (10U << 10) /* IPG Receive Time 1 */ +#define E1000_TIPG_IPGR2_DEF (10U << 20) /* IPG Receive Time 2 */ /* E1000_REG_RAH */ -#define E1000_RAH_AV (1 << 31) /* Address Valid */ +#define E1000_RAH_AV (1U << 31) /* Address Valid */ @@ -236,11 +236,11 @@ C_ASSERT(sizeof(E1000_TRANSMIT_DESCRIPTOR) == 16); /* E1000_PHY_STATUS */ -#define E1000_PS_LINK_STATUS (1 << 2) +#define E1000_PS_LINK_STATUS (1U << 2) /* E1000_PHY_SPECIFIC_STATUS */ -#define E1000_PSS_SPEED_AND_DUPLEX (1 << 11) /* Speed and Duplex Resolved */ +#define E1000_PSS_SPEED_AND_DUPLEX (1U << 11) /* Speed and Duplex Resolved */ #define E1000_PSS_SPEEDSHIFT 14 -#define E1000_PSS_SPEEDMASK (3 << E1000_PSS_SPEEDSHIFT) +#define E1000_PSS_SPEEDMASK (3U << E1000_PSS_SPEEDSHIFT)