lywsvip/reactos
1
0
Fork 0
mirror of https://github.com/reactos/reactos.git synced 2026-05-24 00:00:41 +08:00
Code Issues Packages Projects Releases Wiki Activity

[SDK] Add some more AVX-512 definitions (#8565)

Browse Source 
Add some more Intel AVX-512 extension definitions to the SDK,
as I saw several newer ones were missing. No functionality or purpose yet.

Should be useful for implementing full support in the future.

Reference: Intel Instruction Extensions Set Programming guide,
starting from page 24: https://cdrdv2.intel.com/v1/dl/getContent/671368
This commit is contained in:
Peter Eik
2026-03-02 21:52:32 +01:00
committed by GitHub
parent 1d3f99a87a
commit 391f7cae5b
1 changed files with 35 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
sdk/include/reactos/x86x64/Intel/Cpuid.h
View File

@@ -1490,7 +1490,24 @@ typedef union {
/// RDPKRU/WRPKRU instructions).
///
UINT32 OSPKE : 1;
UINT32 Reserved8 : 8;
UINT32 Reserved8 : 1;
///
/// [Bit 6] AVX512_VBMI2.
///
UINT32 AVX512_VBMI2 : 1;
UINT32 Reserved : 3;
///
/// [Bit 10] AVX512_VPCLMULQDQ.
///
UINT32 AVX512_VPCLMULQDQ: 1;
///
/// [Bit 11] AVX512_VNNI.
///
UINT32 AVX512_VNNI : 1;
///
/// [Bit 12] AVX512_BITALG.
///
UINT32 AVX512_BITALG : 1;
///
/// [Bit 13] If 1, the following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE,
/// IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.
@@ -1549,18 +1566,31 @@ typedef union {
/// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.)
///
UINT32 AVX512_4FMAPS : 1;
UINT32 Reserved : 4;
///
/// [Bit 14:4] Reserved.
/// [Bit 8] AVX512_VP2INTERSECT.
///
UINT32 Reserved4 : 11;
UINT32 AVX512_VP2INTERSECT : 1;
///
/// [Bit 14:9] Reserved.
///
UINT32 Reserved4 : 6;
///
/// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid part.
///
UINT32 Hybrid : 1;
///
/// [Bit 25:16] Reserved.
/// [Bit 22:16] Reserved.
///
UINT32 Reserved5 : 10;
UINT32 Reserved : 7;
///
/// [Bit 23] AVX512_FP16.
///
UINT32 AVX512_FP16 : 1;
///
/// [Bit 25:24] Reserved.
///
UINT32 Reserved5 : 2;
///
/// [Bit 26] Enumerates support for indirect branch restricted speculation
/// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors