From 06cbc2acd28d376af4ea377f339e69b4005f1ea0 Mon Sep 17 00:00:00 2001
From: Dmitry Borisov <di.sean@protonmail.com>
Date: Tue, 28 Jul 2020 00:25:18 +0600
Subject: [PATCH] [BOOTVID] More improvements for PC-98 (#2936)

- Fix failure handling
- Reduce memory mapping that's not needed
---
 drivers/base/bootvid/i386/pc98/bootvid.c | 37 +++++++++++++++++-------
 sdk/include/reactos/drivers/pc98/video.h |  2 ++
 2 files changed, 28 insertions(+), 11 deletions(-)

diff --git a/drivers/base/bootvid/i386/pc98/bootvid.c b/drivers/base/bootvid/i386/pc98/bootvid.c
index c938910e957..18af07764a6 100644
--- a/drivers/base/bootvid/i386/pc98/bootvid.c
+++ b/drivers/base/bootvid/i386/pc98/bootvid.c
@@ -11,8 +11,8 @@
 
 /* GLOBALS ********************************************************************/
 
-static ULONG_PTR VideoMemoryI;
-ULONG_PTR FrameBuffer;
+static ULONG_PTR PegcControl = 0;
+ULONG_PTR FrameBuffer = 0;
 
 #define PEGC_MAX_COLORS    256
 
@@ -25,23 +25,38 @@ GraphGetStatus(
     UCHAR Result;
 
     WRITE_PORT_UCHAR((PUCHAR)GRAPH_IO_o_STATUS_SELECT, Status);
-    KeStallExecutionProcessor(1);
     Result = READ_PORT_UCHAR((PUCHAR)GRAPH_IO_i_STATUS);
 
     return (Result & GRAPH_STATUS_SET) && (Result != 0xFF);
 }
 
+static BOOLEAN
+TestMmio(VOID)
+{
+    USHORT OldValue, NewValue;
+
+    OldValue = READ_REGISTER_USHORT((PUSHORT)(PegcControl + PEGC_MMIO_MODE));
+
+    /* Bits [15:1] are not writable */
+    WRITE_REGISTER_USHORT((PUSHORT)(PegcControl + PEGC_MMIO_MODE), 0x80);
+    NewValue = READ_REGISTER_USHORT((PUSHORT)(PegcControl + PEGC_MMIO_MODE));
+
+    WRITE_REGISTER_USHORT((PUSHORT)(PegcControl + PEGC_MMIO_MODE), OldValue);
+
+    return !(NewValue & 0x80);
+}
+
 static BOOLEAN
 HasPegcController(VOID)
 {
     BOOLEAN Success;
 
     if (GraphGetStatus(GRAPH_STATUS_PEGC))
-        return TRUE;
+        return TestMmio();
 
     WRITE_PORT_UCHAR((PUCHAR)GDC2_IO_o_MODE_FLIPFLOP2, GDC2_EGC_FF_UNPROTECT);
     WRITE_PORT_UCHAR((PUCHAR)GDC2_IO_o_MODE_FLIPFLOP2, GDC2_MODE_PEGC_ENABLE);
-    Success = GraphGetStatus(GRAPH_STATUS_PEGC);
+    Success = GraphGetStatus(GRAPH_STATUS_PEGC) ? TestMmio() : FALSE;
     WRITE_PORT_UCHAR((PUCHAR)GDC2_IO_o_MODE_FLIPFLOP2, GDC2_MODE_PEGC_DISABLE);
     WRITE_PORT_UCHAR((PUCHAR)GDC2_IO_o_MODE_FLIPFLOP2, GDC2_EGC_FF_PROTECT);
 
@@ -212,8 +227,8 @@ InitializeDisplay(VOID)
     WRITE_PORT_UCHAR((PUCHAR)GDC2_IO_o_MODE_FLIPFLOP2, GDC2_MODE_PEGC_ENABLE);
     WRITE_PORT_UCHAR((PUCHAR)GDC2_IO_o_MODE_FLIPFLOP2, GDC2_MODE_LINES_800);
     WRITE_PORT_UCHAR((PUCHAR)GDC2_IO_o_MODE_FLIPFLOP2, GDC2_EGC_FF_PROTECT);
-    WRITE_REGISTER_USHORT((PUSHORT)(VideoMemoryI + PEGC_MMIO_MODE), PEGC_MODE_PACKED);
-    WRITE_REGISTER_USHORT((PUSHORT)(VideoMemoryI + PEGC_MMIO_FRAMEBUFFER), PEGC_FB_MAP);
+    WRITE_REGISTER_USHORT((PUSHORT)(PegcControl + PEGC_MMIO_MODE), PEGC_MODE_PACKED);
+    WRITE_REGISTER_USHORT((PUSHORT)(PegcControl + PEGC_MMIO_FRAMEBUFFER), PEGC_FB_MAP);
 
     /* Select the video source */
     RelayState = READ_PORT_UCHAR((PUCHAR)GRAPH_IO_i_RELAY) & ~(GRAPH_RELAY_0 | GRAPH_RELAY_1);
@@ -348,8 +363,8 @@ VidInitialize(
     PHYSICAL_ADDRESS BaseAddress;
 
     BaseAddress.QuadPart = VRAM_NORMAL_PLANE_I;
-    VideoMemoryI = (ULONG_PTR)MmMapIoSpace(BaseAddress, VRAM_PLANE_SIZE, MmNonCached);
-    if (!VideoMemoryI)
+    PegcControl = (ULONG_PTR)MmMapIoSpace(BaseAddress, PEGC_CONTROL_SIZE, MmNonCached);
+    if (!PegcControl)
         goto Failure;
 
     if (!HasPegcController())
@@ -366,8 +381,8 @@ VidInitialize(
     return TRUE;
 
 Failure:
-    if (!VideoMemoryI) MmUnmapIoSpace((PVOID)VideoMemoryI, VRAM_PLANE_SIZE);
-    if (!FrameBuffer) MmUnmapIoSpace((PVOID)FrameBuffer, PEGC_FRAMEBUFFER_SIZE);
+    if (PegcControl)
+        MmUnmapIoSpace((PVOID)PegcControl, PEGC_CONTROL_SIZE);
 
     return FALSE;
 }
diff --git a/sdk/include/reactos/drivers/pc98/video.h b/sdk/include/reactos/drivers/pc98/video.h
index 35a5f704b75..6c20b26cfcd 100644
--- a/sdk/include/reactos/drivers/pc98/video.h
+++ b/sdk/include/reactos/drivers/pc98/video.h
@@ -22,6 +22,8 @@
 #define PEGC_FRAMEBUFFER_PACKED  0xF00000
 #define PEGC_FRAMEBUFFER_SIZE    0x080000
 
+#define PEGC_CONTROL_SIZE        0x000200
+
 /* High-resolution machine */
 #define VRAM_HI_RESO_PLANE_B     0xC0000
 #define VRAM_HI_RESO_PLANE_G     0xC8000